This invention relates to a semiconductor integrated circuit chip including a Hall element connected to a differential amplifier and, more particularly, to such an integrated circuit having a low offset output voltage.
The integrated Hall element is typically comprised of a PN-junction-isolated thin epitaxial region of N-type having a pair of oppositely disposed ohmic contacts by which a constant energizing voltage may be established through the epitaxial Hall element region along one Hall axis, and another pair of oppositely disposed output ohmic contacts lying in another axis of the Hall region having a direction at right angles to the one axis. A Hall voltage appears at the output contact having a magnitude and polarity corresponding to that of the magnetic field in the Hall element which is orthogonal to the two Hall axes.
When the Hall element is employed as a sensor of magnetic fields, it is usually important that the Hall output voltage be zero when the orthogonal magnetic field is zero. However, it has been impossible to manufacture Hall elements with a zero off-set voltage and efforts to understand and reduce or compensate Hall-element off-set voltage span two decades.
A primary requirement for low offset voltage is symmetry of the ohmic contacts about the two Hall element axes. But, even with perfect symmetry an offset voltage exists due to physical stresses in the integrated circuit that may have been built in during processing or imposed by a surrounding protective package.
Occassionally, an integrated Hall-element having a near zero offset voltage may be produced, but not reproducibly and usable because the stress-related causal factors have fortuitously been of such an opposing and cancelling effect.
Responding to this situation, there have been devised many offset-voltage compensating schemes. In general, these schemes are based upon a means for introducing a measured amount of asymmetry in the operation of the Hall element by an external circuit adjusting means. One approach is to add another energizing-current contact not in the one axis and supplying therethrough an offset-voltage adjusting current. Another and more varied approach supplied an offset-voltage adjusting current through just one of the existing Hall-element output contacts. In both approaches, the adjustment of the offset adjusting current is made for each integrated Hall-element after its manufacture.
Representative of the unbalanced energizing current approach is that described in the IBM Technical Disclosure Bulletin, Vol. 21, No. 7, December 1978, pages 2717-2718. In the patent to Avery and Higgs, U.S. Pat. No. 4,465,976 issued Aug. 14, 1984 that is assigned to the same assignee as is the present invention, there is described an integrated Hall-element representative of the unbalanced Hall-element output current approach.
In the copending application to Higgs and Humenick to be issued as U.S. Pat. No. 4,578,692 on Mar. 25, 1986, and assigned to the same assignee as is the present invention, there is described a direct approach to reducing stress related offset voltage in an integrated Hall element. There, an array of four Hall cells are included having their outputs connected in parallel and having opposing energizing currents so that the offset voltage of one is offset by that of another and the composite offset voltage is thereby notably reduced as was known in the prior art, However, the four Hall-cells acting as one Hall element in this patent are surrounded by a wide PN-junction isolated moat that further reduces the generation of an offset voltage by isolating the four self compensating cells from the surrounding circuits wherein unsymmetrically doped regions inducing internal stresses in the semiconductor substrate are prevented from creating unsymmetrical stresses on the quad Hall element.
It is an object of the present invention to further reduce and to better control the offset voltage of an integrated circuit including a quad Hall element and Hall-voltage amplifer.